DEPARTMENT OF Electronics and Communication

Educational Qualification:

• PhD—Model Engineering College, KTU (2023)
• M Tech – Anna University (2012)
• B-Tech—Marian Engg College, Thiruvananthapuram (2010)

Specialization

• Semiconductor Devices /Chip Design

Current Research Interest

• AI Hardware
• Mixed Signal Circuit Design

Professional Body Member

• IEEE Member:93068329

Publications

1. Arun A V, Minu K K, Sreelekshmi P S, Jobymol Jacob. Drain Current Modeling of Tunnel FET using Simpson’s Rule. Silicon 14, 5931–5939 (2022). https://doi.org/10.1007/s12633-021-01328-5
2. Arun, A. V., P. S. Sreelekshmi, and Jobymol Jacob. “Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors.” Microelectronics Journal 124 (2022): 105433. https://doi.org/10.1016/j.mejo.2022.105433
3. A. V, Sruthi. K. S and Jobymol. Jacob, “Dual Material Gate Tunnel Field Effect Transistor based Dopingless 1T DRAM,” 2021 International Conference on Communication, Control and Information Sciences (ICCISc), 2021, pp. 1-5
4. A. V, et. al, “Development and Analysis of Convolutional Neural Network based Accurate Speech Emotion Recognition Models,” 2022 IEEE 19th India Council International Conference (INDICON)).
5. A. V, Ria M and Jobymol. Jacob, “Gate Tunable Thermionic Tunnel FET with  n+ Pocket,” 2018 IEEE 17th India Council International Conference (INDICON), 2018, pp. 1-6
6. Tharian, J., Nandakrishnan, R., Sajesh, S., Arun, A.V. and Jayadas, C.K., 2022, November. Automatic Emotion Recognition System using tinyML. In 2022 International Conference on Futuristic Technologies (INCOFT) (pp. 1-4). IEEE
7. L. Manuvel and Arun. A.V., “Simple Accurate Carry Prediction Adder For RAC Unit In DCT Computing Of Image Processing,” 2019 IEEE 16th India Council International Conference (INDICON), 2019, pp. 1-4
8. Arun, A.V. and Jacob, J., 2023. Modeling and Simulation of Dual Material Double Gate Tunnel FETs. In Tunneling Field Effect Transistors (pp. 53-72). CRC Press
9. Arun, A.V., Sreelekshmi, P.S. and Jacob, J., 2023. State of the Art Tunnel FETs for Low Power Memory Applications. Advanced Ultra Low‐Power Semiconductor Devices: Design and Applications, pp.131-163.
10. Arun, A.V., Sajeesh, M., Jacob, J. and Ajayan, J., 2024. An overview of DC/RF performance of nanosheet field effect transistor for future low-power applications. Advanced MOS Devices and their Circuit Applications, pp.1-24.

Professional Experience

• Teaching Experience: 9 Years.
• Research Experience: 8 months