🎉 VLSI Excellence at MITS! 🎉
The Department of Electronics and Communication Engineering (ECE), Muthoot Institute of Technology and Science (MITS), proudly celebrates a remarkable achievement with two research papers accepted for VLSID 2027, the 40th International Conference on VLSI Design, to be held in Bengaluru, India.
🏆 Paper 1: Decision Faults in Mixture-of-Experts Accelerators: Witness-Checked Routing on a RISC-V Platform
Authors: Binu Manohar, Arun Joy, and Simi Zerine Sleeba
🏆 Paper 2: SCAT-BP: A Selective Compressed-Aware Tagged Hybrid Branch Predictor for FPGA-Based Ibex RISC-V Cores
Authors: Noble G, Sreelakshmy S, and Elza George
These research contributions highlight the department’s commitment to innovation in VLSI design, computer architecture, FPGA-based systems, and dependable hardware design.
👏 Congratulations to the authors and everyone who contributed to this achievement! This recognition reflects the department’s continued dedication to research excellence and technological advancement.
View MoreAs part of an international faculty exchange, Dr. Abhilash Antony (HOD of ECE at MITS) met with leadership and international relations teams at ESIGELEC School of Engineering in France to strengthen research partnerships, academic collaborations, and global mobility. During the visit, Dr. Antony also reconnected with the 2025–26 batch of MGCER–ESIGELEC International Master's Program students as they begin their academic and cultural journey in Rouen.
Paper accepted for VLSID 2027
International Faculty Exchange Initiative Between MITS and ESIGELEC School of Engineering
Patent on “ESTIMATING INDOOR LOCATION WITH MAGNETIC FIELD AND RSSI VALUES USING MACHINE LEARNING”
🎉 VLSI Excellence at MITS! 🎉
The Department of Electronics and Communication Engineering (ECE), Muthoot Institute of Technology and Science (MITS), proudly celebrates a remarkable achievement with two research papers accepted for VLSID 2027, the 40th International Conference on VLSI Design, to be held in Bengaluru, India.
🏆 Paper 1: Decision Faults in Mixture-of-Experts Accelerators: Witness-Checked Routing on a RISC-V Platform
Authors: Binu Manohar, Arun Joy, and Simi Zerine Sleeba
🏆 Paper 2: SCAT-BP: A Selective Compressed-Aware Tagged Hybrid Branch Predictor for FPGA-Based Ibex RISC-V Cores
Authors: Noble G, Sreelakshmy S, and Elza George
These research contributions highlight the department’s commitment to innovation in VLSI design, computer architecture, FPGA-based systems, and dependable hardware design.
👏 Congratulations to the authors and everyone who contributed to this achievement! This recognition reflects the department’s continued dedication to research excellence and technological advancement.
As part of an international faculty exchange, Dr. Abhilash Antony (HOD of ECE at MITS) met with leadership and international relations teams at ESIGELEC School of Engineering in France to strengthen research partnerships, academic collaborations, and global mobility. During the visit, Dr. Antony also reconnected with the 2025–26 batch of MGCER–ESIGELEC International Master's Program students as they begin their academic and cultural journey in Rouen.